1. Field of the Invention
The present invention relates to a Viterbi decoder for performing maximum likelihood decoding of convolutional codes using a Viterbi algorithm. More particularly, the present invention relates to an analog Viterbi decoder wherein at least a part of the aforementioned decoding process is carried out in an analog signal process.
2. Description of Related Art
A Viterbi decoder efficiently searches a plurality of known code sequences using a Viterbi algorithm to find a path of a code sequence which is at the shortest code distance from a received code sequence from among the plurality of known code sequences, to output a decoded signal corresponding to the path found. The Viterbi decoders are, for example, used for error correction in satellite communication systems, since the decoder has great error correction capability.
Conventionally, the Viterbi decoders have been realized only by digital signal processing, as described, for example, in U.S. Pat. Nos. 4,614,933 and 4,763,328.
Increasing the constraint length K of a convolutional code improves the error correction capability of the Viterbi decoder. However, increasing the constraint length exponentially increases the physical size of the decoder. A large scale integrated circuit is usually employed to realize a Viterbi decoder having such a large scale construction. Nevertheless, a decoder using a TTL circuit construction is not easily realized because the circuit scale is not so easily reduced and power consumption is very large in the TTL circuit. On the other hand, the power consumption of a circuit having a CMOS circuit construction is not so large, and therefore, the decoder can be realized by a several-chip construction using CMOS circuits.
The CMOS circuit construction, however, can not be applied when a high speed operation of more than 20 to 30 Mbps is required, since a maximum operation speed of the CMOS circuit is around that level. In this case an ECL circuit construction may be applied. However, the decoder constructed by the ECL circuit cannot be miniaturized because the power consumption of the ECL circuit is greater than that of the TTL circuit. Thus, a high speed Viterbi decoder having greater error correction capability has not been realized in a relatively small size using only digital signal processing.
Soft decision decoding is usually employed in the Viterbi decoder rather than hard decision decoding. In the soft decision decoding, a demodulated base band signal is quantized into a digital value in a plurality of quantization levels and the code distance is estimated in the form of the digital values. In this case, the coding gain of the Viterbi decoder is improved if the number of quantization levels is increased. The number of quantization levels is, however, actually limited, because the complexity of the circuit is increased as the number of quantization levels is increased.